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mc34921 rev 5.0, 07/2005 freescale semiconductor technical data ? freescale semiconductor, in c., 2005. all rights reserved. *this document contains information on a product under development. specifications and information herein are subject to change without notice. configurable motor driver ic with power supplies the 34921 power ic integrates mult iple motor drivers, multiple power regulators, and most other analog functions a small consumer motion-enabled product needs. the 34 921?s circuitry is fully protected with current limiting, short-circuit shutdown, over-temperature, over- voltage, and under-voltage detection. supervisory functions can be read and programmed through a 8-mhz serial interface. a 5.0 v dual-mode (linear or swit ching) voltage regulator, 3.3 v switching buck regulator, and a voltag e-selectable (1.5 v, 1.8 v, 2.5 v) linear regulator provide power management. two h-bridges and a configurable motor driver are provi ded for controlling two dc motors and one unipolar stepper motor. the highly integrated 34921 brings together sensing, communication, power management, system protection, and motor control in one device. features ? two functionally identical pulse-width modulated (pwm) dc motor drivers ? one switching, one linear, and one dual-mode regulator ? dual mode switching/linear 5.0 v regulator ? supervisory functions (power-on reset and error reset circuitry) ? 8-channel, 8-bit analog-to-digital converter (adc) ? charge pump for high-side mosfet drive ? complete support for ? analog quadrature encoder ? pb-free package is designated by suffix ae figure 1. 34921 simplified application diagram h-bridge motor driver and power supply 34921 ordering information device temperature range (t a ) package mc34921ae/r2 0c to 70c 64 lqfp-ep ae suffix (pb-free) 98arh98426a 64-lead lqfp-ep b+ b+ 34921 gateout 5.0 v 3.3 v vcore serial ports a/d inputs sa/cdcma sb/lsout1 sa/cdcmb sb/lsout2 b+ mcu 5.0 v / 3.3 v high-side mosfet b a a b step motor b+ miso mosi sclk ce cpwma cpwmb dc moto r adcma adcmb apwm dc moto r bdcma bdcmb bpwm dgnd gnd an0 an3 a b c
analog integrated circuit device data 2 freescale semiconductor 34921 internal block diagram internal block diagram figure 2. 34921 simplifi ed internal block diagram supervisor circuitry rst gate driver gateout vboost cp2 cp1 charge pump gate voltage generator 5 v 5 v supply 5 v switch 5 v select 5.0 v dual mode regulator vcore select vcore vcore supply v core linear regulator 3.3 v 3.3 v switch b+ 3.3 v switching regulator an0/analogout_a an1/analogout_b an2/analogin_a an3/analogin_b a/d converter and multiplexer i/v converter enc_filta enc_filtb gnd serial i/o dgnd b+ ce sclk mosi miso cpwma/cdcpwm cpwmb sb /lsout2 s b/lsout1 sa /cdcmb s a/cdcma active clamp step motor driver cdcmb/hsout2 cdcma/hsout1 ss dc motor driver adcmb motor driver a b+ adcma apwm bdcmb motor driver b b+ bdcma bpwm thermal shutdown oscillator
analog integrated circuit device data freescale semiconductor 3 34921 terminal connections terminal connections figure 3. terminal function description table 1. terminal function description a functional description of each terminal can be found in the functional terminal description section beginning on page 18 terminal terminal name formal name definition 1, 16, 17, 24, 32, 33, 41, 48, 49, 64 gnd ground ground. 2 vcore select core voltage output select core voltage regulator output voltage select. 3s a/cdcma unipolar step a/ dc motor c output a step motor output a or dc motor c output a. 4sa /cdcmb unipolar step a / dc motor c output b step motor output a or dc motor c output b. 5s b/lsout1 unipolar step b/ low-side 1 step motor output b or low-side output 1. 6sb /lsout2 unipolar step b / low-side 2 step motor output b or low-side output 2. 7, 20, 21, 28, 29, 62 b+ power supply input motor and regulator input voltage. 8, 9, 25, 40, 57 nc no connect no internal connection to this terminal. gnd vcore select s a/cdcma 3.3v switch 3.3 v vcore supply vcore adcma adcma gnd sb /lsout2 b+ nc nc sa /cdcmb s b/lsout1 gnd enc_filta enc_filtb 5 v 5 v supply 5 v switch 5 v select bdcma bdcma gnd an1/analogout_b an0/analogout_a gnd nc an3/analogin_b an2/analogin_a gnd cdcma/hsout1 b+ cpwma/cdcpwm ce sclk mosi miso rst gnd apwm cpwmb nc dgnd cdcmb/hsout2 bpwm gnd adcmb adcmb cp1 gateout b+ b+ bdcmb bdcmb gnd vboost cp2 gnd nc b+ b+ 2 3 10 11 12 13 14 15 16 6 7 8 9 4 5 17 18 19 26 27 28 29 30 31 32 22 23 24 25 20 21 48 47 46 39 38 37 36 35 34 33 43 42 41 40 45 44 64 63 62 55 54 53 52 51 50 49 59 58 57 56 61 60 1
analog integrated circuit device data 4 freescale semiconductor 34921 terminal connections 10 3.3 v switch 3.3 v switching regulator switch output 3.3 v regulator switching output. 11 3.3 v 3.3 v regulator feedback feedback terminal for 3.3 v switching regulator and internal logic supply. 12 v core supply core voltage regulator input core regulator input supply. 13 v core core voltage regulator output core regulator output voltage. 14, 15 adcma dc motor a output a dc motor driver a output a. 18, 19 adcmb dc motor a output b dc motor driver a output b. 22 vboost boost voltage boost voltage storage node. 23 cp2 switching capacitor 2 charge pump capacitor connection 2. 26 cp1 switching capacitor 1 charge pump capacitor connection 1. 27 gateout high-side mosfet gate driver gate driver for external n-channel switch. 30, 31 bdcmb dc motor b output b dc motor driver b output b. 34, 35 bdcma dc motor b output a dc motor driver b output a. 36 5 v select 5.0 v regulator mode select 5.0 v regulator operating mode select. 37 5 v switch 5.0 v switching regulator switch output 5.0 v switching regulator switching output. 38 5 v supply 5.0 v regulator input supply 5.0 v regulator input voltage. 39 5 v 5.0 v regulator feedback 5.0 v regulator feedback. 42 an0/analogout_a an0/analogout_a a/d input 0 or analog encoder output a. 43 an1/analogout_b an1/analogout_b a/d input 1 or analog encoder output b. 44 an2/analogin_a an2/analogin_a a/d input 2 or analog encoder input a. 45 an3/analogin_b an3/analogin_b a/d input 3 or analog encoder input b. 46 enc_filtb analog encoder channel b filter i/v amplifier channel b filter. 47 enc_filta analog encoder channel a filter i/v amplifier channel a filter. 50 rst reset reset input and output. 51 miso master in slave out serial data out to mcu. 52 mosi master out slave in serial data in from mcu. 53 sclk serial clock serial data clock. table 1. terminal function description (continued) a functional description of each terminal can be found in the functional terminal description section beginning on page 18 terminal terminal name formal name definition
analog integrated circuit device data freescale semiconductor 5 34921 terminal connections 54 ce chip enable serial data strobe. 55 cpwma/cdcpwm motor driver c pwm input a step motor driver phase a pwm or dc motor driver pwm. 56 dgnd digital ground digital ground. 58 cpwmb motor driver c pwm input b step motor driver phase b pwm. 59 apwm motor driver a pwm input pwm input for dc motor driver a. 60 bpwm motor driver b pwm input pwm input for dc motor driver b. 61 cdcmb/hsout2 motor driver c dc motor output or high- side output 2 step motor driver c output or high-side output 2. 63 cdcma/hsout1 motor driver c dc motor output or high- side output 1 step motor driver c output or high-side output 1. table 1. terminal function description (continued) a functional description of each terminal can be found in the functional terminal description section beginning on page 18 terminal terminal name formal name definition
analog integrated circuit device data 6 freescale semiconductor 34921 maximum ratings maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol max unit electrical ratings input power supply voltage i b+ = 0.0 a b+ -0.3 to 38 v logic input voltage v in -0.3 to v 5.0 +0.3 v boost supply voltage v boost b + +15 v input power supply ripple voltage ripple voltage measured at < 20 mhz v rippleb 400 mv pp motor drivers a & b maximum output voltage v outmax 40 v 5.0 v linear regulator maximum output voltage startup v 5.0 5.4 v 5.0 v switching regulator maximum output voltage startup v 5.0 5.4 v 3.3 v switching regulator maximum output voltage startup v 3.3 3.6 v vcore linear regulator maximum output voltage i core =0.0a v core v core_nom +10% v motor drivers a, b, and c (motor driver c configured as step motor driver) (1) motor driver a sink or source current motor driver b sink or source current motor driver c sink or source current i pwm (a) i pwm (b) i pwm (c) 4.5 4.5 1.5 a motor driver c in step mode step motor output current output x or x on i step 2.0 a motor driver c in step mode standoff voltage output off, i dss = 10 ma v bvds 60 v esd voltage (2) non-operating, unbiased, human body model machine model charge device model v esd 2000 200 250 v notes 1. b+ = 34 v, motor stalled and saturated 2. esd testing is performed in accord ance with the human body model (c zap = 100 pf, r zap = 1500 ? ), the machine model (c zap = 200 pf, r zap = 0 ? ), and the charge device model.
analog integrated circuit device data freescale semiconductor 7 34921 maximum ratings thermal ratings operating temperature ambient junction t a t j 0.0 to 70 150 c storage temperature t stg -55 to 150 c thermal resistance junction to ambient (3) junction to board (4) junction to case r ja r jb r jc 40 14 <1.0 c/w peak package reflow temperature during solder mounting (5) t solder 245 c thermal resistance and package dissipation ratings power dissipation (t a = 25 c) (6) p d 2.0 w notes 3. 1s pcb test board jesd51-2 and semi g38-87. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured at the pac kage center lead foot. 2s2p test board, exposed pad soldered to pcb. 5. terminal soldering temperature limit is for 10 seconds maxi mum duration. not designed for imme rsion soldering. exceeding thes e limits may cause malfunction or permanent damage to the device. 6. maximum power dissipation at indicated ambient temperature in free air with no heatsink used. table 2. maximum ratings(continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol max unit
analog integrated circuit device data 8 freescale semiconductor 34921 static electrical characteristics static electrical characteristics table 3. static electr ical characteristics characteristics noted under conditions 16 v b+ 34 v, 0 c t a 70 c, and 0 c t j 100 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit serial interfaces (miso, mosi, sclk, ce ) input low voltage from mcu v 5.0 = 5.0 v, v 3.3 = 3.3 v, i in < 200 a, v in falling v il 1.11.352.2 v input high voltage v 5.0 = 5.0 v, v 3.3 = 3.3 v, i in < 200 a, v in rising v ih 1.12.002.2 v input hysteresis v 5.0 = 5.0 v, v 3.3 =3.3v v hys 0.4 0.6 1.5 v output high-level, miso (v 5.0 = 5.0 v, v 3.3 =3.3v) i out = 150 a i out =20 a v oh (miso) 2.4 v 3.3 -0.1 v 3.3 -25 mv v 3.3 -10 mv v 3.3 v 3.3 v output low-level, miso (v 5.0 =5.0v, v 3.3 =3.3v) i out < 20 a i out < 150 a v ol (miso) 0.0 0.0 10 25 100 400 mv input pulldown current v 5.0 = 5.0 v, v 3.3 = 3.3 v, v in = 5.0 v, includes rst i pulldown 50 120 175 a miso high-impedance current miso = 3.3 v or gnd i hi-z -100 0.1 100 a 5.0 v linear regulator logic supply voltage i v5.0 = 10 ma to 50 ma, 16 v < b+ < 20 v, r ext = 140 ? v 5.0 4.8 5.0 5.2 v load regulation i load = 10 ma to 50 ma v iload ?? 100 mv current limit threshold r ext = 0 ? i limit 75 135 600 ma v 5.0 to turn on/off v 3.3 regulator (7) v 5_3.3 t ?2.2 ? v hysteresis for v 5_3.3 t (7) v 5_3.3 t _ hys ? 175 ? mv notes 7. see figure 10, power-up sequencing , page 22 .
analog integrated circuit device data freescale semiconductor 9 34921 static electrical characteristics 5.0 v switching regulator vreg threshold v 5.0 4.8 5.0 5.2 v cycle-by-cycle curr ent limit threshold v 5.0 = 2.0 v to max v 5.0 1.0 v i limit 0.75 ? 1.2 1.0 2.25 ? a v 5.0 to turn on/off v 3.3 regulator (8) v 5_3.3 t ?2.2 ? v hysteresis for v 5_3.3 t (8) v 5_3.3 t _ hys ? 175 ? mv 3.3 v switching regulator vreg threshold v 3.3 3.15 3.28 3.45 v cycle-by-cycle curr ent limit threshold v 3.3 = 2.0 v to max v 3.3 1.0 v i limit 2.75 ? 3.6 3.5 5.5 ? a vcore 3.3v linear regulator voltage tolerance i core = 0.02 a to 0.3 a, v nom =2.5v i core = 0.02 a to 0.3 a, v nom =1.8v i core 0 0.02 a to 0.3 a, v nom =1.5v v core_tol 2.35 1.675 1.4 2.49 1.78 1.49 2.66 1.925 1.6 v load regulation i load =20ma to 300ma v iload ? 10 100 mv current limit threshold i limit 400 750 1200 ma motor drivers in dc mode motor driver a high- or low-side switch voltage drop i pwm = 1.7 a, gnd or b+ to output v drop (a) ?.65 1.5 v motor driver a output current limit i limit (a) 3.6 4.9 7.2 a motor driver b high- or low-side switch voltage drop i pwm = 2.0 a, gnd or b+ to output v drop (b) ?.70 1.4 v motor driver b output current limit i limit (b) 2.8 4.9 7.2 a motor driver c high- or low-side switch voltage drop i pwm = 0.375 a, gnd or b+ to output v drop (c) ?.75 1.5 v motor driver c current limit?top side i limit1 (c) 0.75 1.2 1.5 a motor driver c current limit?bottom side i limit2 (c) 1.0 1.65 2.0 a notes 8. see figure 10, power-up sequencing , page 22 . table 3. static electrical characteristics (continued) characteristics noted under conditions 16 v b+ 34 v, 0 c t a 70 c, and 0 c t j 100 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 34921 static electrical characteristics motor drivers in dc mode (cont) output mosfet leakage current v gs = 0.0 v, v o = 0.0 v or 20 v i dss ?0.1 40 a current limit maximum duty cycle (9) idc limit 1.0 2.0 4.0 % current limit pulse width (9) i limitpw 0.5 1.5 6.0 s motor driver c in step mode switch voltage drop, output to ground i step = 0.375 a, gnd to output v sdrop ??1.5 v step motor current limit b+ = 20 v i step (limit) 1.0 ? 2.0 a voltage at which internal clamp activates i dss = 1.0 ma, b+ = 20 v v clamp 44 51 59 v tested maximum high-voltage leakage current v s = v clamp +4.0 i breakdown ?0.5 40 a any step driver output leakage current to ground b+ = 20 v, v s = 20 v i leakage ?0.1 40 a current limit maximum duty cycle td ilimit 5.0 11 15 % current limit pulse width i limitpw 510 20 s v b charge pump boost voltage i b = 0.5 ma v b b + +10 b + +11.5 b + +15 v external n-fet gate drive output gateout high output i oh = 4.0 ma i oh = 200 a v oh2 v b -6.0 v b -0.3 v b -2.5 v b -.1 v b v b v gateout low output i ol = -200 a v ol ?0.1 0.3 v notes 9. motor driver a, b, c top side only. for c bottom side, see mo tor driver c in step mode: current limit maximum duty cycle and current limit pulse width table 3. static electrical characteristics (continued) characteristics noted under conditions 16 v b+ 34 v, 0 c t a 70 c, and 0 c t j 100 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 34921 static electrical characteristics supervisor circuitry minimum function b+ for c harge pump, oscillator up reset/fault registers valid (10) b+ 9.0 ? ? v minimum function v 5.0 for rst operational rst v ol 0.05 v @ 1.0 ma (10) v 5.0 rst 2.0 ? ? v minimum function v 3.3 for rst operational rst v ol 0.05 v @ 1.0 ma (10) v 3.3 rst 2.0 ? ? v rst low voltage (11) i rst 5.0 ma v ol ? 0.1 0.25 v rst v 5.0 threshold v 5.0 rising v 5.0 falling v 5.0 t+ v 5.0 t ? ? 4.5 4.65 4.6 4.75 4.70 v rst hysteresis for v 5.0 v hysv5.0 10 50 ? mv rst v 3.3 threshold v 3.3 rising v 3.3 falling v 3.3 t+ v 3.3 t ? ? 2.8 2.9 2.9 3.15 3.0 v rst hysteresis for v 3.3 v hys_3.3 10 15 ? mv rst v core threshold v core falling v core 85 86 90 %v core_ nom rst hysteresis for v core v hys core ? 10 ? mv overtemperature junction temperature (12) t j rising t j (over) 140 ? ? c overtemperature hysteresis (12) t j falling t j (hys) 10 ? 30 c thermal warning (12) t w t j -30 ? t j -20 c b+ undervoltage threshold to assert rst v 5.0 = +5.0 v, b+ falling b+ (fault) 12 12.75 13.5 v b+ undervoltage threshold hysteresis (13) b+ fault (hys) 1.0 1.5 2.0 v minimum b+ necessary to clear b+ fault v 5.0 = +5.0 v, b+ rising b+ recovery ? ? 15.25 v notes 10. if any of these conditions for this not is true, then rst is activated until all operating conditions are met. 11. the rst terminal uses an external pull-up, which may be to 5.0 v or 3.3 v. 12. guaranteed by design. 13. alternately, the minimum b+ fault threshold voltage must not be lower than 12 v, and the b+ fault clear voltage must not be h igher than 15.25 v. the hysteresis may be greater than 2.0 v if this requirement is met. table 3. static electrical characteristics (continued) characteristics noted under conditions 16 v b+ 34 v, 0 c t a 70 c, and 0 c t j 100 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 34921 static electrical characteristics analog encoder interface curren t-to-voltage conversion stage minimum offset current i offset_min -6.0 -8.0 -10 a midpoint offset current i offset_mid -0.5 0.0 0.5 a maximum offset current i offset_max 6.0 8.0 10 a offset step size (1 lsb) i offstep 0.25 0.5 0.75 a analog-to-digit al converter resolution, no missing codes adc ? ? 8.0 bits measurement range for correct conversion imr 0.0 ? 5.0 v linearity error (16) over input voltage range of 4% to 96% ideal measurement range (imr) max. over time and temperature (14) , (15) v in = -0.5 to 5.5 v (17) i nl ? 0.4 1.0 lsb ? input leakage current (anx) v 5.0 = 5.0 v, t j = 25 c, v anx = 5.0 v, analog_test mode = 0, channel not selected i leakage ? 0.1 10 a notes 14. errors include effects of multiplexer and sample and hold circuitry, including droop. 15. the linearity error is the worst case error caus ed by the differential and integral nonlinearity. 16. an lsb (least significant bi t) is defined as follows: 17. the adc will read full scale at v in = 5.0 v. if v in on one input exceeds this value, the va lue of other inputs may become unreadable. table 3. static electrical characteristics (continued) characteristics noted under conditions 16 v b+ 34 v, 0 c t a 70 c, and 0 c t j 100 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit lsb = imr 2 #bits -1 volts where: imr is the ideal measurement range. #bits is the resolution of the adc.
analog integrated circuit device data freescale semiconductor 13 34921 static electrical characteristics analog-to-digital converter (cont) zero error (18) , (19) e z ? 1.0 8.0 lsb (20) zero error drift over time and temperature (18) e zd ? 4.0 ? lsb full scale error (18) , (19) , (21) e fs ? 2.0 8.0 lsb notes 18. errors include effects of multiplexer and sample and hold circuitry, including droop. 19. the zero error is defined as the number of lsb values away from the ideal value of 1/2 lsb that the adc output count will tr ansition from 0 to 1 when the input is swept through the range of inte rest. the transition must occur within the specified range. 20. an lsb is defined as follows: 21. the full scale error is defined as the num ber of lsb values away from the ideal val ue of -1/2 lsb from full scale that the a dc output count actually transitions from -1 lsb count to full scale c ount when the input voltage is swept through the voltage range of i nterest. the transition must occur within the specified range. table 3. static electrical characteristics (continued) characteristics noted under conditions 16 v b+ 34 v, 0 c t a 70 c, and 0 c t j 100 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit 1 03 2 5 47 6 000 001 010 011 100 101 110 111 output code input voltage zero error ideal transfer characteristic actual transfer characteristic 1 03 2 5 47 6 000 001 010 011 100 101 110 111 output code input voltage full scale error ideal transfer characteristic actual transfer characteristic 1 03 25 47 6 000 001 010 011 100 101 110 111 output code input voltage differential nonlinearity 1 03 2 5 47 6 000 001 010 011 100 101 110 111 output code input voltage integral nonlinearity lsb = imr 2 #bits -1 volts where: imr is the ideal measurement range. #bits is the resolution of the adc.
analog integrated circuit device data 14 freescale semiconductor 34921 dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electr ical characteristics characteristics noted under conditions 16 v b+ 34 v, 0 c t a 70 c, and 0 c t j 100 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit serial interface timing (22) setup time for ce to rising edge of sclk (c l = 50 pf) t setup ( ce ) 15 ? ? ns hold time for ce after rising edge of sclk (c l = 50 pf) t hold ( ce ) 15 ? ? ns setup time for mosi to rising edge of sclk (c l = 50 pf) t setup (mosi) 15 ? ? ns hold time for mosi after rising edge of sclk (c l = 50 pf) t hold (mosi) 15 ? ? ns delay for miso valid after rising edge of sclk (c l = 50 pf) t delay (miso) ? 35 55 ns period for sclk (c l = 50 pf) t period (sclk) 125 ? 750 ns duty cycle of sclk t duty (sclk) 45 ? 55 % 5.0 v switching regulator switching rise and fall time load resistance = 100 ? , b+ = 18 v t r , t f 10 30 50 ns 3.3 v switching regulator switching rise and fall time load resistance = 100 ? , b+ = 18 v t r , t f 10 16 50 ns motor drivers motor drivers a and b output waveform rise time r = 7.0 ? , v dcx = (5.0 v) to (0.90 x b+), b+ = 18 v t r 100 175 300 ns motor driver c output waveform rise time r = 25 ? , v dcx = (5.0 v) to (0.90 x b+), b+ = 18 v t r 100 175 300 ns output waveform fall time v dcx = (0.90 x b+) to 5.0 v, r = 7.0 ? , b+ = 18 v t f 100 ? 300 ns crossover dead time (23) t dead 15 600 2000 ns motor driver c in step mode output rise time v xphase = 5.0 v to 0.90 x b+, r w = 20 ? , b+ = 18 v t r 100 175 350 ns output fall time v xphase = 0.90 x b+ to 5.0 v, r w = 20 ? , b+ = 18 v t f 100 155 350 ns delay from phase turn-off to counterphase turn-on r w = 20 ? , 0.90 x b+ rising to 0.90 x b+ falling, b+ = 18 v falling t delay (c) 0.0 300 400 ns notes 22. see figure 4, serial interface timing , page 16 . 23. this parameter is guaranteed by design but not production tested.
analog integrated circuit device data freescale semiconductor 15 34921 dynamic electrical characteristics supervisor circuitry rst delay v 5.0 = +4.9 v (24) t delay (rst ) 128 ? 128 t sclk rst filter time v 5.0 = 5.0 v t filter ? 3.25 ? s rst fall time v 5.0 = 5.0 v, c l = 100 pf, i pullup = 0.75 ma(external), 90% to 10% of v 5.0 t f ? 7.0 20 ns external input low to rst pulled low v 5.0 = 5.0 v (25) t slpl ? 26 60 ns analog encoder interface variable gain stage adjustable gain (ideal) settings s = 0 to 15, default 0 settings s = 16 to 31, default 0 g (ideal) (1.0+0.1 * s) (1.0+0.1 * [s-16]) / 0.375 gain setting = 0 setting = 31 g 0.8 6.0 1.0 6.6 1.2 7.2 v/v gain step factor tolerance gain step size gs/g(s- 1 ) s = 1 to 31 gsf 1.01 1.02 1.2 v/v analog encoder interface digital signal conversion stage operating frequency f op(max) 0 ? 15 khz comparator filter time (24) filter configuration bit set to 0 filter configuration bit set to 1 t filter 3.0 6.0 ? ? 4.0 7.0 sclk cycles adc sample and hold acquisition time a/d speed bit = 0 a/d speed bit = 1 t sh 15 31 ? ? 16 32 t sclk conversion time (return word cloc ked out immediately following t c ) a/d speed bit = 0 a/d speed bit = 1 t c ? ? ? ? 48 96 t sclk master oscillator operating frequency b+ 12 v f op 150 200 250 khz notes 24. guaranteed by design. 25. see figure 6, rst timing , page 17 . table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 16 v b+ 34 v, 0 c t a 70 c, and 0 c t j 100 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 34921 timing diagrams timing diagrams figure 4. serial interface timing figure 5. step motor crossover delay timing t delay (c) a or b output a or b output 90% b+ 90% b+
analog integrated circuit device data freescale semiconductor 17 34921 timing diagrams figure 6. rst timing external rst input v ih v il 34921 rst v ih v il t slpl t delay (rst )
analog integrated circuit device data 18 freescale semiconductor 34921 functional description introduction functional description introduction the serial interface of the mc34921 is a three input, one output interface similar to a serial peripheral interface (spi) port in general form, but different in specific clocking requirements due to the fact that an a/d converter cannot reliably run without a continuous clock. the 34921 serial interface communicates to a micr ocontroller unit (mcu) at up to 16 mhz. the serial signals are sclk, ce , mosi, and miso. the sclk signal pin requires a free-running clock (up to 16 mhz) which is provided by the mcu. this signal is required to ensure proper oper ation of both the adc and the reset timer circuitry. the serial data transfers between the mcu and the 34921 via the mosi and miso terminals. the serial data from the mcu is handled in the mc34921 via two input registers -- the normal in put register contains bits controlling the motor drivers as well as the a/d converter, and the config register contains bits relating to the general configuration setup of the device. the mc34921 also has two output registers -- the normal output register reports a/d conversion data as well as digi tal encoder data, and the ireq output register reports under vo ltage, temperature, and other device status data. functional terminal description ground (gnd) main ground. it is used for t he b+ filters and motor filter grounds, as well as the ground return for external components which are used wi th the linear and switching regulators. cover voltage output select (vcore select) this terminal is used to select the output voltage provided by the vcore linear regulator. the vcore select potential is latched in during the mc34921's power-on sequence. the mc34921 will not respond to changes in vcore select after power up. unipolar step a/dc motor c output a (s a/ cdcma) a low-side driver output is configurable for either stepper motor control (s a) or c dc motor (as cdcma, which requires an external hardwire to pin 63) via the serial i/o. the driver is pwm cont rolled via the cpwma/cdcpwm pin, and direction controlled via the serial i/o. it includes an active voltage clamp, current limit, and thermal shutdown protection. unipolar step a /dc motor c output b (sa / cdcmb) a low-side driver output is configurable for either stepper motor control (sa ) or c dc motor (as cdcmb, it requires external hardwire to pin 61) via the serial i/o. the driver is pwm controlled via the cpwma/cdcpwm pin, and direction controlled via the serial i/o. it includes active voltage clamp, current limit, and thermal shutdown protection. unipolar step b/low-side 1 (s b/lsout1) a low-side driver output is configurable for either stepper motor control (s b) or as a general purpose low-side driver (lsout1) via the serial i/o. the s b is pwm controlled via the cpwmb pin. the direction and lsout1 are controlled via the serial i/o. it includes active voltage clamp, current limit and thermal shutdown protection. unipolar step b /low-side 2 (sb /lsout2) a low-side driver output is co nfigurable for either stepper motor control (sb ) or as a general purpose low-side driver (lsout2) via the serial i/o. the sb is pwm controlled via the cpwmb pin. the direction and lsout2 are controlled via the serial i/o. it includes active voltage clamp, current limit and thermal shutdown protection. power supply input (b+) this is the main power supply input for the regulators and dc motor drivers. 3.3 v switching regulator switch output (3.3 v switch) the high-side driver output is used for the 3.3v switching regulator. it uses the internal 200khz clock. 3.3 v regulator feedback (3.3 v) this terminal is the error amp feedback for the 3.3v switching regulator. it is also the output point for the 3.3v switching supply. core voltage regulator input (vcore supply) the input voltage terminal for the vcore linear supply, which is usually provided by externally hardwiring the 3.3v switching regul ator output. core voltage regulator output (vcore) the output terminal of the vcore linear regulator. voltage options of 1.5v, 1.8v, or 2.5v are set by the potential of the vcore select pin at power up. it features current limit
analog integrated circuit device data freescale semiconductor 19 34921 functional description functional terminal description and thermal shutdown protection. it is typically used to supply a micro processor core or embedded dram. dc motor a output a (adcma) a high-side and low-side driver output terminal, which when combined with adcmb forms the a h-bridge dc motor driver. the driver is pwm controlled via the apwm input, and direction controlled via the serial i/o. it features current limit and thermal shutdown protection. dc motor a output b (adcmb) a high-side and low-side driver output terminal, which when combined with adcma forms the a h-bridge dc motor driver. the driver is pwm controlled via the apwm input and direction controlled via the serial i/o. it features current limit and thermal shutdown protection. boost voltage (vboost) this is the boost voltage st orage node for the charge pump circuit. it provides the gate drive voltage for the high-side fets in the dc motor drivers, switch mode controllers, and gateout pin. swtiching capacitor (cp1 and cp2) these are the connections for the charge pump flying capacitor. high-side mosfet gate driver (gateout) the output terminal for an external n-channel high-side driver. enabled via the serial i/o, it provides gate drive control for an external n-cha nnel mosfet high-side switch. dc motor b output b (bdcmb) a high-side and low-side driver output terminal, which when combined with bdcmb, forms the b h-bridge dc motor driver. the drivers are pwm controlled via the bpwm input, and direction controlled via the serial i/o. it features current limit and thermal shutdown protection. dc motor b output a (bdcma) a high-side and low-side driver output terminal, which when combined with bdcma, forms the b h-bridge dc motor driver. the drivers are pwm controlled via the bpwm input, and direction controlled via the serial i/o. it features current limit and thermal shutdown protection. 5.0 v regulator mode select (5 v select) this terminal is used to set t he 5v regulator to operate in either linear or switching mode. ground this terminal to operate in switching mode, or float to operate in linear mode. 5.0 v regulator switch output (5 v switch) this terminal is the high-side driver output used for the 5v switching regulator. it uses the internal 200khz clock. 5.0 v regulator input supply (5 v supply) the input voltage terminal for th e 5v regulator. limit it to 20v in linear mode. an additional series resistor is recommended to dissipate power off-chip. 5.0 v regulator feedback (5 v) this is the 5v feedback input terminal and output voltage point for the 5v regulator when in the switch configuration, and the output pin when tied to 5v switch in linear configuration. it is also t he power supply terminal for the mc34921ae on board logic. an0/analogout_a (an0/analogout_a) mux input 0 for the a/d converter, which is also available in freescale test mode as an output for the an2 i/v converter. an1/analogout_b (an1/analogout_b) mux input 1 for the a/d converter, which is also available in freescale test mode as an output for the an3 i/v converter. an2/analogin_a (an2/analogin_a) mux input 2 for the a/d converter incorporating an i/v converter with offset and gain calibration via the serial i/o. an3/analogin_b (an3/analogin_b) mux input 3 for the a/d converter incorporating an i/v converter with offset and gain calibration via the serial i/o. analog encoder channel b filter (enc_filtb) input to the an3 i/v converter stage for feedback components used with the i/v converter op amp. analog encoder channel a filter (enc_filta) input to the an2 i/v converter stage for feedback components used with the i/v converter op amp. reset (rst) supervisory function i/o, incorporating a comparator input and an open drain output, and typically connected to the rst of a microprocessor. as an input, rst resets internal registers to default states, turns step motor outputs off, forces dc motor drive low-side drives on, and sets miso to a high z state. as an output, rst is set during b+ uvlo, all regulators uvlo, current limit , and thermal shutdown events. master in slave out (miso) this is the master-in-slave-out terminal; the serial output port of the serial i/o, which ty pically connects to the miso of a microprocessor. miso reports two data frames: normal
analog integrated circuit device data 20 freescale semiconductor 34921 functional description functional terminal description - a/d conversion and analog encoder signals, and info - fault data and analog encoder signals. the output data is loaded into the output shift register on each rising edge of sclk, while ce is held in a logic high state. this means the miso pin shows the status of the most significant bit (bit 15) of the output frame until the first rising edge of sclk after the ce pin is taken to a logic low state. the shift register will then shif t data out on the miso pin on each subsequent rising edge of sclk while ce is held in the logic low state. during transfers, the most significant bit (msb) is transferred first. after all 16 bits have been transferred, if any additio nal clocks are given while ce is in a logic low state, the data is undefined and should be ignored. master out slave in (mosi) this is the master-out-slave-i n terminal; the serial input port of the serial i/o, which typically connects to the mosi of a microprocessor. it has two fr ames of operation - normal and config, which are set by a bit in the normal frame.the mosi pin is used for serial instruction data input. mosi information is clocked into the input shift register on the rising edge of sclk. a logic high state present on mosi will program a register bit on. the s pecific bit will turn on with the 16th rising edge of sclk after placing the ce pin in a logic low state. conversely, a logic low state present on the mosi pin will program the register bit off. the specific bit will turn off with the 16th rising edge of sclk after placing the ce pin in a logic low state. for each rising edge of the sclk while ce is logic low, a data bit instructio n (on or off) is loaded into the shift register per the data bit mo si state. the last bit clocked in (bit 0) is the config bit. if this bit is in a logic high state at the 16th rising edge of sclk after lowering the ce pin, the bits in the shift register will be loaded into the config register. if the bit is in a low logic state, the bits will be loaded into the normal register. care should be taken to keep the mosi pin in a logic low state when it is not being used for transfers to avoid erroneous da ta. during transfers, the most significant bit (msb) is clocked in first. serial clock (sclk) as the serial clock termina l, the sclk pin clocks the internal shift registers of th e mc34921. the serial data input (mosi) pin data is latched into the input shift register on the rising edge of the 16th clock after the falling edge of the chip select (ce ) pin. the serial data out put (miso) pin shifts data out of the shift register on the rising edge of the sclk signal. false clocking of the shift register must be avoided to ensure validity of data. it is essentia l that one rising edge of sclk occur while ce is in a logic high state to ensure the correct output data is latched into the output shift register. clocking the sclk pin for more than one clock period while ce is in a logic high state is not recommended and may have undesired effects. for this reason, it is recommended that the sclk pin be clocked only once while ce is in a logic high state. the mc34921 is designed such that sclk should be a continuous clock. this ensure s that a/d sample rates are held as constant as possible. chip enable (ce) the chip enable port of the serial i/o, typically connects to the ce of a microprocessor. the logic state of the ce pin activates clocking in and shifting out of data in and out of the mc34921. while the ce pin is in the logic high state, the output data in the normal re gisters and the info registers are latched (depending on the state of the ireq bit in the previous communication frame) in on each rising edge of the clock such that the state of t he msb (bit 15) is readable on the serial data output (miso) pin. when ce is in a low logic state both the input shift register and output shift register shift data at the rising edge of sclk. motor driver c pwm input a (cpwma / cdcpwm) this is the pwm logic input for the s a/sa /cdcm motor drivers. the motor driver outputs follow this signal. motor driver c pwm input b (cpwmb) this is the pwm logic input for the s b/sb motor drivers. the motor driver outputs follow this signal. digital ground (dgnd) this terminal is used for the serial i/o and a/d converter logic grounds, and should be kept isolated from the analog ground on the application pcb. motor driver a pwm input (apwm) the pwm logic input terminal fo r the adcm motor drivers. the motor driver outputs follow this signal. motor driver b pwm input (bpwm) the pwm logic input terminal fo r the bdcm motor drivers. the motor driver outputs follow this signal. motor driver c step motor output or high-side output 2 (cdcmb / hsout2) the high-side driver output is configurable for either c dc motor control (as cdcmb, it requires external hardwire to pin 4), or as a general purpose high-side driver (hsout2) via the serial i/o. the cdcmb is pwm controlled via the cpwma/ cdcpwm pin. the direction and hsout2 are controlled via the serial i/o. it includes current limit and thermal shutdown protection. motor driver c step motor output or high-side output 1 (cdcma / hsout1) the high-side driver output is configurable for either c dc motor control (as cdcma, it requires external hardwire to pin 4), or as a general purpose high-side driver (hsout1) via the serial i/o. the cdcma is pwm controlled via the cpwma/ cdcpwm pin. the direction and hsout1 are controlled via the serial i/o. it includes current limit and thermal shutdown protection.
analog integrated circuit device data freescale semiconductor 21 34921 functional description functional internal block description functional internal block description figure 7. internal block diagram 5.0 v and 3.3 v regulators the 34921 5.0 v regulators have two operating modes? switching and linear?that shar e a dedicated input terminal, as illustrated in figure 8 and figure 9 . the 5.0 v switching regulator operates off b+ directly. the 5.0 v linear regulator is only used when b+ < 20 v, and the dedicated input terminal is connected to b+ through an external power resistor to dissipate some power off-chip. the regulator that is used depends on the power requirement and b+ nom of the application. the designer is able to trade off power versus overall system cost for each partic ular applicati on. the linear regulator mode is a low-current mode and has much less external component cost. figure 8. 5.0 v switching regulator mode figure 9. 5.0 v linear regulator mode the 5v select terminal must be tied to ground for switching regulator mode. an internal pull-up is incorporated in the 34921 sufficient to avoid any problems owing to switching noise on this terminal. the 5.0 v switching and linear regulators may supply external logic components of the overall assembly, depending on the application. for the 5.0 v linear regulator, an external capacitor on the output should be used for filtering. 5.0 v and 3.3 v switching regulators the 5.0 v and 3.3 v switchin g regulators are implemented as constant ripple buck regulat ors. these regulators operate in both discontinuous and continuous mode. the clock source is the on-board 200 khz master oscillator. the actual frequency of the switch term inal can vary owing to cycle skipping. the switch mosfet is internal to the 34921 ic, but the remaining components?rec overy diode, inductor, and output capacitor?must be externally supplied. the input voltage to the regulators is b+, and the regulators perform within specifications over the range of i 5.0 0.6 a for the 5.0 v switching regulator and i 3.3 2.5 a for the 3.3 v switching regulator. each has c ycle-by-cycle current limiting. 5.0 v regulator switching and charge pump dc motor drivers timing logic step motor driver v core linear regulator a/d convertor linear 3.3 v regulator switching supervisory rst function 34921 5v supply 5v 5v switch 5v select b+ 34921 5v supply 5v 5v switch 5v select b+ r r = b+ - 9.0 v i out
analog integrated circuit device data 22 freescale semiconductor 34921 functional description functional internal block description the power up sequence of the 5.0 v and 3.3 v switching regulators is controlled such that -1.0v <= v5 - v3.3 <= 2.6v. figure 10 depicts the power-up sequence for the 5.0 v and 3.3 v regulators. figure 10. power-up sequencing vcore linear regulator the output voltage of the vcore linear regulator is selectable for different applicat ions. the output is selected with an external pull-up or pull-d own, which instructs internal logic to select the appropriate regulator set- point (refer to table 5 ). the vcore linear regulator is available whenever the 3.3 v supply is in stable operation. current limiting is implemented to provide short circuit protection. the vcore linear regulator is shut off by the local thermal shutdown sensor, thus protecting the 34921 ic from an over-temperature condition re sulting from a vcore short circuit, but otherwise allowing vcore to follow the 3.3 v switching regulator. the vcore supply terminal is the drain or collector of the linear regulator transistor and must be tied to the 3.3v terminal to use the internal regulator. this allows the option of using an external regulator if the internal 3.3 v regulator cannot supply enough current for a particular application. use of an external regulator requires leaving this terminal open, thus disabling the internal regulator. the output of the external regulator is then connected to the vcore terminal for under-voltage monitoring. dc motor drivers there are two dc motor drivers on the 34921 ic: if used in a printer application, for example, they might be the carriage motor driver and the paper motor driver. a third drive, motor driver c, can be configured as a dc motor driver or, when b+ nom = 18 v, as a step motor driver (refer to succeeding paragraph step motor driver ). configuration bit 13 determines the mode: 0 = step mode, 1 = dc mode. a step motor driver can only be used in b+ = 12 v to 20 v applications. step motor outputs are suppressed by the internal supervisor for b+ > 20 v. the ability to use the low- side mosfets for general purpose low-side outputs is included when the system is in dc motor mode (lsoutx). alternatively, the ability to use the high-side mosfets for general purpose high-side outputs (hsoutx) has been included when the system is in step mode. (refer to table 20 , page 31 , and table 21 , page 32 .) the dc motor drivers are pulse width modulated (pwm?d) via inputs from the digital subsystem on the apwm and bpwm terminals, respectively. this signal is approximately 20 khz to 40 khz. the dc motor driver bridge direction may be reversed while there is significant current flowing in the motor. the purpose of this action is to brake the motor by rapidly lowering the current. there are pull-downs on the pwm input terminals so that, in the event of a connection failure, the driver will default to a safe condition. the dc motor drivers provide high-side and low-side current limiting. the cu rrent limits have a 0.5 s to 6.0 s deglitch filter, followed by an o ff-timer. the off-timer shuts off the bridge long enough to meet the 4% duty cycle goal. the motor drivers also have thermal shutdown protection. step motor driver c step motor driver c can be configured as a dc motor driver or, when b+ nom = 18 v, as a step motor driver (refer to succeeding paragraph step motor driver ). configuration bit 13 determines the mode: 0 = step mode, 1 = dc mode. the ability to use the low-side mosfets for general purpose low-side outputs is included wh en the system is in dc motor mode (lsoutx). alternatively, th e ability to use the high-side mosfets for general purpose high-side outputs (hsoutx) has been included when the system is in step mode. (refer to table 20 , page 31 , and table 21 , page 32 .) power-up 5.0 v reg on ref = 2.5 v 3.3 v reg off 5.0 v fault 5.0 v reg on 3.3 v reg off 3.3 v start 3.3 v reg on ref = 2.5 v 5.0 v reg on full start 3.3 v reg on ref = 5.0 v 5.0 v reg on 3.3 v positive threshold 3.3 v positive threshold v 5.0 v 5_3.3t & 3.3 v > 3.3 v uv v 5.0 < v 5_3.3 t v 5.0 v 5_3.3t 5.0 v 3.3 v v 5.0 v 5_3.3t undervoltage (uv) table 5. v core regulator output voltage select v core select v core_nom (volts) tied to ground terminal 1.5 tied to 3.3v terminal 1.8 floating 2.5
analog integrated circuit device data freescale semiconductor 23 34921 functional description functional internal block description step motor driver c is pwm?d via an input from the digital subsystem on the cpwma/cdcpw m terminal. this signal is approximately 20 khz to 40 khz. there are pull-downs on the pwm input terminals so that dc motor drive c will default to a safe condition in the event of a connection failure. step motor driver a step motor driver can be conf igured as a dc motor driver (refer to preceding paragraph dc motor drivers ) or, when b+ nom 20 v, as a unipolar step driver. serial input configuration frame bit 4 de termines the mode: 0 = step mode, 1 = dc mode. a step motor driver will only be used in b+ = 12 v to 20 v applications. note it is possible to use the step motor driver with b+ > 20 v if the step motor is driven from a separate supply that is 20 v. the step motor driver on t he 34921 is a unipolar, voltage- mode wave drive circuit employing synchronous rectification. the centertap of each phase-count erphase pair is connected to b+. two pwm signals are sent directly from the digital subsystem. the cpwma/cdcpwm terminal provides the pwm signal for the a and a outputs. the cpwmb terminal provides the pwm signal for the b and b outputs. the step motor driver employs synchronous rectification to control substrate currents. in synch ronous rectification, when an output is turned off, the counterphase output mosfet is turned on to maintain current continuity. in order to avoid a large shoot-through current, there is a dead time delay (t delay ) between phase off and counterphase on. refer to figure 5, step motor crosso ver delay timing , page 16 . vboost charge pump the high-side mosfets in the dc motor h-bridges and the external gateout switch need a gate voltage in excess of b+, which is provided by the vboost supply. the vboost regulator is a charge pump, switching directly off the b+ supply and operating at 200 khz. external n-fet gate drive output the gateout terminal is an output for a high-side n-channel mosfet gate drive. the output will be used to drive an external high-side mosfet switch (see figure below). when enabled, gateout will be connected to the v b supply. the edge rates when switching the transistors must be controlled so that shoot-through current does not affect b+. figure 11. external n-fet gate drive circuit clocking schemes there are two basic clocking schemes that can be used while clocking data into the mc34921 ic. one has 16 rising edges of sclk while ce is in a logic low state and the other has 15 rising edges of sclk. in the 15 sclk clocking scheme, the input data and output data are latched on the same clock edge. in the timing diagram on page 16 , the numbers on the mosi line are the bits that will be clocked into the input shift register at the rising edge of sclk. they are drawn occurring before sclk to account for the required setup time (minimum 15ns). the numbers on the miso line are the bits that will be clock ed out at the rising edge of sclk. they are drawn occurring after sclk to account for the output delay from the rising edge of sclk (maximum 40ns). the numbers on the sclk line are for reference only. note: when using the 15 bit clocking method with exactly one rising edge of sclk when ce is in a logic high state, the output data to be sent out is latched at the same time the ireq bit is latched in. the next frame following the assertion of the ireq bit is the ireq data. i.e., the frame after the sending of the ireq bit will have the data from the ireq register rather than skipping one frame. note: regarding the reporting of the done bit after the completion of an a/d conversion: the done bit is sent out every time a conversion completes. this requires the user to hold the mosi pin in a low state when it is not being us ed to transmit data. refer to figure 4, serial interface timing and figure 5, step motor crossover delay timing supervisory (rst) function supervisory circuitry the supervisor circuitry provides control of the rst line, an open drain signal, based on system operating conditions monitored by the 34921 ic. v 5.0 , v 3.3 , v core , b+, and thermal shutdown detectors in various parts of the chip are monitored for error conditions. because other devices in the system may trigger a reset, the rst line itself is also monitored, but the s upervisor circuitry controls all reset timing, including externally generated resets. driving the rst line low causes the system to be held in the reset state. v 5.0 , v b gateout b+ r s c s gateout bit
analog integrated circuit device data 24 freescale semiconductor 34921 functional description functional internal block description v 3.3 , v core , b+, and tsd have both positive- and negative- going thresholds. static operating specifications the state of rst is guaranteed as long as the minimum supervisor operating conditions of b+ 9.0 v and v 5.0 2.0 v and v 3.3 1.5 v and v core are met. once all these conditions are met, rst is dependent on system operating conditions. during initial power-up, rst is held low if any one of the following error conditions is present: +5.0 v(low), v core (low), +3.3 v(low), b+(low), or tsd. once all voltages reach their positive-going threshold, rst is set high after the appropriate timing. dynamic operating specifications the rst is a bidirectional signal with an open drain output driver and a cmos digital input gate (see figure 12 ). this i/ o structure allows wired or connection to the cpu?s rst i/ o terminal, as well as allowing the cpu to initiate a reset cycle by driving its rst terminal low. when responding to a cpu request for a reset cycle, the 34921 ic must respond rapidly enough to prevent a glitch. figure 6, rst timing , page 17 , shows the timing parameters for responding to an externally applied rst signal. figure 12. rst terminal interface the rise time with the open drain circuit may be relatively slow, and the internal rst input gate must operate reliably (no oscillations during the trans ition) under these conditions; i.e., the rst input can be inhibited for up to t phsl (max). error conditions must be present for a minimum time, t filter , before the 34921 responds to them. once all error conditions are cleared, rst is held low for an additional time of t delay , 128 sclk periods. if any monitored item falls below its negative-going threshold for t filter , 1.5 s to 5.0 s, the t delay count is restarted when system operating conditions are met, regardless of whether the t delay count has been completed. the trigger for the t delay retriggerable one shot is ([+5.0 v(low) + 3.3 v(low) + v core (low) + b+(low) + tsd] and t filter ), where t filter is the 1.5 s to 5.0 s delay. rst and thermal shutdown state (tsd) definition there are seven registers in the info output word where the trigger for the reset is recorded. this includes externally generated resets as well as all t he fault conditions listed in the supervisory functions sectio n of this datasheet. these registers will remain valid as long as b+ 9.0 v. the fault registers will only be cleared upon an externally generated rst and will not be guaranteed for b+ < 9.0 v; i.e., initial power-up or a serious b+ fault. the ext bit will only be set upon an externally generated reset. whenever rst is asserted and tsd is not set, the miso terminal will enter a high-impedan ce state, all the step motor outputs will be off, and all the dc motor low-side drives will be on. in addition, all internal data registers excepting the rst fault registers in the info output word will be set to their default values. the thermal shutdown circuitry will monitor the chip?s internal temperature at various points. the overtemperature circuitry will disable all circuitry on the 34921 ic with the exception of the rst output. rst will be asserted when the temperature exceeds 140c. this condition will be maintained (regulators shut down in accordance with table 6 , page 24 ) until the die temperature falls by the thermal hysteresis amount, at which time the 5.0 v and 3.3 v regulators will restart and the supervisor circuit will issue a full length reset pulse. the system will then perform a normal restart. the purpose of this circuitry is to prevent damage to the 34921 owing to inadvertent high dissipation in the motor drivers. table 6. regulator shutdown schedule analog encoder interface introduction the analog encoder interface is intended to provide a complete interface for an analog quadrature encoder, such as an agilent technologies heds-9710/heds-9711 series of analog output small optical encoder modules. from internal reset circuits to internal registers rst c load optional condition xdcma (26) xdcmb (26) s x sx 5.0 v v core 3.3 v fault registers other data registers rst 0 0 off off on on on updated at falling rst default value tsd and rst z z off off off on off updated at falling rst default value tsdcore and rst z z off off off off off updated at falling rst default value notes 26. xdcma and xdcmb: 0 means low-side on, 1 means high-side on, z means both off.
analog integrated circuit device data freescale semiconductor 25 34921 functional description functional internal block description the agilent heds-9710/heds-9711 incremental analog quadrature encoder is a 200 l pi encoder that outputs a quadrature analog current reflecting the position of the encoder codewheel/codestrip wit hin the encoder. the analog encoder interface must provide six functions to support this encoder: force a bias point of 1.3 v, current-to-voltage conversion, offset current nulli ng, output amplitude adjust (variable gain), channel inversion, and digital phase generation (see figure 13 ). note: freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in this document. while freescale offers component recommendations, it is the customer?s responsibility to validate their application. figure 13. analog encoder interface block diagram i/v conversion stage the i/v conversion stage is carried out by a transimpedance amplifier using an external resistor. there is a resistor to ground at the analogin_x input to allow offset current trim and force the proper bias point on the encoder. the feedback resistor should be sized to accommodate 2.5 v output voltage swing for the full encoder current waveform. for example, if the encoder produces a 50 a signal, the feedback resistor needs to be 50 k ? . the resistor to ground must have a specific relationship to the feedback resistor. it needs to be 1.17 times the feedback resistor, or 58.5 k ? for the example above. this ensures that the encoder is biased at 1.35 v, and that the output of the transimpedance amplifier is 2.5 v. the i/v conversion stage can trim an encoder offset current of up to 8.0 a in the encoder output. variable gain amplifier the i/v conversion stage is followed by a variable gain amplifier that can compensate for variations in the encoder output. this is designed to accommodate manufacturing variations in the encoder, as we ll as aging and other effects. the gain can be changed over the serial interface at any time. the output of the variable gain amplifiers can be routed to the analogout_x terminals for engineering evaluation. otherwise, these terminals are general purpose a/d inputs. channel inversion and digital phase generation the a and b channels are inverted by applying the function channelx = 2.5 v - channelx. this results in four signals: a, b, a , and b . these signals are used produce the digital encoder signals denca and dencb, which are converted by the adc to provide the analog position information. the value of the denca and dencb signals determine which signal?a, b, a , or b ?is converted. refer to table 7 , page 26 , for more information. position information the entire position information is produced by concatenating the value of the a quadrature counter, driven by denca and dencb bits, and the 8 bits of ?fractional? information from the adc. calibration of the encoder it is necessary to adjust the gain and offset of the i/v circuit initially and periodically to compensate for encoder-to- encoder variation, aging, and ot her effects. the adc ?double conversion? function allows this by continuously sampling the a and b signals, allowing a map of the encoder output to be built up. the user will need to provide the necessary algorithm to use the waveform map to produce gain and offset calibration values for both channels. analog-to-digital converter introduction there is an 8-bit analog-to-digital converter (adc) on the 34921 ic that uses the on-b oard voltage reference and derives all the necessary timing signals from the sclk input. the adc is referenced to the same ground as the system ground (gnd). adc input selection the adc has an 8-channel analog multiplexer so that all inputs share one adc. the input(s) to be converted are to adc a a to serial interface denca dencb to adc a b b b b a variable gain amplifier variable gain amplifier enc_filta enc_filtb 1.3 v an3/analogin_b -1 -1 an2/analogin_a
analog integrated circuit device data 26 freescale semiconductor 34921 functional description functional internal block description determined by the a/da[2 : 0] bits in the serial normal input frame (refer to table 11 , page 28 ). three different types of conversion can occur (refer to table 7 ): ? single conversion 00x does a single conversion of inputs an0/analogout_a or an1/analogout_b. ? double conversion 1xx does a double conversion of channels a and b, a and a , b and b , or an2/analogin_a and an3/analogin_b, respectively. ? auto-select conversion 011 does a single conversion of one of the outputs from the analog encoder interface, as select ed by the digital outputs of the analog encoder interface, denca and dencb. table 7. a/d input conversion channel addressing a/d conversion flow there is a start conversion bit in the serial channel. the presence of this bit begins a conversion cycle on the input(s) selected in that frame. if the adc is converting when a subsequent start bit arrives, this start request will be ignored. figure 14, a/d converter input structure , page 27 , shows how this process works. the current conversion completes during the frame prior to the data being returned. if there is a start bit in that input frame, another conversion is begun as the previous conversion?s data is being shifted out. if there is no start bit in the input frame, then another conversion is begun the frame fo llowing receipt of the start bit. the single conversion rate is paced at four frames for configuration bit 3 =0 or ei ght frames (or less) for configuration bit 3 =1, including sampling time (refer to table 13 , config input frame bit allocation, page 29 ). in order to simplify implementati on of the 34921, the user must ensure that no a/d conversions are in progress when an info word is requested. for i nput pairs, the inputs are listed in the order of conversion in table 7 . normal input frame bit 2 normal input frame bit 3 normal input frame bit 4 normal output frame bit 2 (27) normal output frame bit 3 (27) input(s) selected a/da0 a/da1 a/da2 denca dencb 0 0 0 x x an0/analogout_a terminal 100x x an1/analogout_b terminal 1101 0 analog encoder interface output a 1100 1 analog encoder interface output a 1101 1 analog encoder interface output b 1100 0 analog encoder interface output b 101x x analog encoder interface outputs a and a with s/h (28) 001x x analog encoder interface outputs a and b with s/h (28) 011x x analog encoder interface outputs b and b with s/h (28) 111x x an2/analogin_a and an3/analogin_b terminals (direct input) with s/h (28) notes notes 27. denca and dencb values are captured at the output of the 3 or 6 edge filter on sclk rising edge, then immediately shifted out in the miso data when ce is high. 28. inputs are listed in order of conversion.
analog integrated circuit device data freescale semiconductor 27 34921 functional description functional internal block description a/d converter input structure the input impedance of a selected channel is an rc circuit. as shown in figure 14 , the input impedance of the selected channel is a resistor connected to the sample and hold (s/h) capacitor. the sample and hold time is 15 * t sclk , or a minimum of 0.9285 s. the tolerances of the internal s/ h components are such that a ti me constant is about 93.6 ns. therefore to achieve a proper level on the s/h capacitor (5*93.6 ns) = 0.468 s, minimum, is re quired to satisfy internal component time constants. this only allows 460 ns for external time constants. therefore, the maximum source impedance of the circuit driving the selected a/d channel is 7.8 k ? when the sclk speed matches the speed configuration bit. figure 14. a/d converter input structure adc output addressing the return word to the digital subsystem also contains two conversion done bits, a/ddone1 and a/ddone2 (refer to table 8 ). the a/ddone1 bit is used for single conversions and the first conversion when input pairs are selected. the a/ddone2 bit is used for the second conversion when input pairs are selected. a zero to one transition of these bits on successive return word s indicates that a conversion cycle is complete and the data sent in that return word is valid for that conversion. the conversion done bits will only be asserted for one serial frame, although the data may be valid for multiple frames. the a/dr bits indicate which a/d input is being reported when data is valid (refer to table 9 ). idle a2ddone1=0 a/da=last address a/dd=last conversion start a2ddone2=0 conversion convert a2ddone1=0 a/da=current a/dd=last a2ddone2=0 conversion start start start done a/da=1 start start conversion done address send data a2ddone1=0 a2da=current a2dd=current a2ddone2=0 conversion address convert2 a2ddone1=0 a/da=current a/dd=last a2ddone2=0 conversion address send data2 a2ddone1=0 a/da=current a/dd=current a2ddone2=1 conversion address note ?start? is bit 1 of the serial in p ut normal frame. table 8. a/d done bits a/ddone1 a/ddone2 return data and a/dr value rising 0 valid for single or first conversion 0 rising valid for second conversion 0 0 don?t care table 9. a/d channel of current a/d data normal output frame bit 4 normal output frame bit 5 normal output frame bit 6 a/d value reported a/dr0 a/dr1 a/dr2 0 0 1 a 1 0 1 b 0 1 1 a 1 1 1 b 0 0 0 an0/analogout_a 1 0 0 an1/analogout_b 0 1 0 an2/analogin_a (direct input) 1 1 0 an3/analogin_b (direct input) i/v i/v channel select logic s/h c < 11.7 pf hold sclk 8-bit adc an0/analogout_a an1/analogout_b an2/analogin_a an3/analogin_b a a b b multiplexer r ds(on) < 8.0 k ?
analog integrated circuit device data 28 freescale semiconductor 34921 functional device operation operational modes functional device operation operational modes normal mode: normal mode is the normal operating mode of the ic (as oppo sed to the configuration mode or information request mode). table 10. normal mode input frame programming model table 11. normal input frame bit allocation (29) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 out2 out1 b b a /cdcb a/cdca adcb adca bdcb bdca gate out a/da2 a/da1 a/da0 start config bit bit name bit description 15? 14 out2, out1 high-side or low-side output control. bit 4 of the co nfiguration mode input frame determines which output is controlled. output turns on when corresponding bit is asserted. refer to table 20 and table 21 truth tables, page 31 and page 32 , respectively, for operation. 13? 10 b ,b, a ,a (31) step motor outputs, inverting. corresponding output on when bit asserted. refer to table 22 truth table, page 32 , for operation. 11? 10 a /cdca, a/cdcb (30) motor driver c direction bits. outputs follow these bi ts, regardless of pwm value, when they are equal; i.e., 00 or 11. refer to table 19 truth table, page 31 , for operation. 9?8 adcb, adca motor driver a direction bits. outputs follow these bi ts, regardless of pwm value, when the are equal; i.e., 00 or 11. refer to table 19 truth table, page 31 , for operation. 7?6 bdcb, bdca motor driver b direction bits. outputs follow these bi ts, regardless of pwm value, when the are equal; i.e., 00 or 11. refer to table 19 truth table, page 31 , for operation. 5 gateout assertion puts v b on the gateout terminal. deassertion c onnects the gateout terminal to ground. 4?2 a/da[2:0] a/d conversion target channel. these bits determine which input(s) to the adc are to be converted. 1 start a/d conversion start bit. this bit causes the adc to sample the input(s) specified by bits a/da[2:0] (bits [4:2]) and begin an analog-to-digital conversion. this bit is ignored if a conversion is already in progress. 0 config the input frame can be either a configuration frame or a normal frame. bit 0 determines the type of frame being received. bit 0 = 0 is a normal mode input frame. notes 29. all defaults = 0 at power up. 30. when in dc motor mode. 31. when in step motor mode, outputs are a, a , b, and b ; when in dc motor mode, outputs b and b have no function.
analog integrated circuit device data freescale semiconductor 29 34921 functional device operation operational modes config mode: configuration mode is the mode in which t he ic is programmed or configured by the external digital subsystem via the serial interface (i.e., mosi, miso, sclk, ce). table 12. config mode input frame programming model table 13. config inpu t frame bit allocation (32) table 14. calibratio n register addressing bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mtest1 mtest0 cal4 (msb) cal3 cal2 cal1 cal0 (lsb) analog _test mode caladdr 1 caladdr 0 filter dc ss a/d speed sleep ireq config bit bit name bit description 15?14 mtest[1:0] reserved for freescale test. set to [10]. 13?9 cal[4:0] data for various calibration registers. 8 analog_test mode routes a and b output of analog encoder interface to an0 and an1, respectively. used only for user development and verification. do not use in normal operation. 7?6 caladdr[1:0] determines the calibration register, as identified in table 14 below, the calibration data in the cal[4:0] (bits 13?9) bits is latched in. 5 filter determines the number of sclk edges used to filter the denca and dencb signals coming from the digital signal generation stage of the analog encoder interface. this digital filter fi lters the denca and dencb signals made available to the serial output frame. 4 dc ss determines if motor driver c operates in dc moto r or step motor mode. implicitly determines whether hsoutx or lsoutx are available. in dc motor mode, lsoutx are available; in step motor mode, hsoutx are available. 3 a/d speed determines how many sclk edges are required for conversi on. this allows the use of a faster sclk but still maintains a/d conversion accuracy. 2 sleep when asserted, causes the 34921 to enter a powe r-down state, and minimize power consumption. 1 ireq causes the next output frame sent to the host to contain internal information from the 34921. 0 config the input frame can be either a configuration frame or a no rmal frame. bit 0 determines the type of frame being received. bit 0 = 1 is a configuration mode input frame. notes 32. all defaults = 0 at power up. caladdr0 caladdr1 register 0 0 channel a gain 1 0 channel a offset 0 1 channel b gain 1 1 channel b offset
analog integrated circuit device data 30 freescale semiconductor 34921 functional device operation operational modes table 15. normal mode output frame programming model table 16. normal mode outp ut frame bit allocation model nfo (ireq) mode: nfo (ireq) mode is the mode in which the mc34921 ic repor ts status and error informat ion via the serial interface. table 17. nfo (ireq) mode output frame programming model i table 18. info (ireq) mode output frame bit allocation bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a/dd7 a/dd6 a/dd5 a/dd4 a/dd3 a/dd2 a/dd1 a/dd0 info a/dr2 a/dr1 a/dr0 dencb denca a/ddone2 a/ddone1 bit bit name bit description 15?8 a/dd[7:0] adc data from last conversion. 7 info identifies the output frame as a normal or information fr ame. the type of output frame is determined by the ireq bit (bit 1) in the configuration mode input frame. 6?4 a/dr[2:0] report the input to the adc that is represented in the a/dd[7:0] (bits 15?8). 3?2 dencb, denca analog encoder interface digital signal s. these signals are used to driv e a quadrature encoder on the mcu. 1?0 a/ddone2, a/ddone1 flag completion of the adc for corresponding conversion. if adc in single conversi on mode, only a/ddone1 is asserted. if in double conversion mode, a/ddone1 is asse rted for first conversion and a/ddone2 is asserted for second conversion bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 1 1 0 ext b+uv info v5vuv 3.3uv coreu v denc b denc a tsd tw bit bit name bit description 15?10 reserved these bits will report [011000]. 9 ext this flag will report if the last generated re set was due to an external signal driving rst . 8 b+uv undervoltage flag for the b+ input voltage. if the input voltage drops below that necessary for the 34921 to operate, this flag will be asserted. 7 info identifies the output frame as a normal or information fr ame. the type of output frame is determined by the ireq bit (bit 1) in the configuration mode input frame. 6 v5vuv undervoltage warning for the 5.0 v regulator. this will be asserted when a fault on the 5.0 v causes the voltage to droop. 5 3.3uv undervoltage warning for the 3.3 v regulator. this will be asserted when a fault on the 3.3 v causes the voltage to droop. 4 coreuv undervoltage warning for the vcore linear regulator. this will be asserted when a fault on the vcore voltage causes the voltage to droop. 3?2 dencb, denca analog encoder interface digital signal s. these signals are used to driv e a quadrature encoder on the mcu. 1 tsd thermal shutdown flag. this flag will report if the last generated reset was due to a tsd. thermal shutdown occurs when the junction temper ature reaches approximately 140oc. 0 tw thermal warning flag. this bit is asserted when t he junction temperature on the die reaches approximately 110oc.
analog integrated circuit device data freescale semiconductor 31 34921 functional device operation logic commands and registers logic commands and registers truth tables use the following notations: for inputs, i limit = 0 means tsd, i limit condition not encountered. i limit = 1 means tsd, i limit condition encountered. for outputs xdcma and xdcmb, 0 means low-side on, 1 means high-side on, z means both off. table 19. dc motors truth table inputs outputs xdca xdcb xdcpwm rst i limit top i limit bottom thermal shutdown (tsd) xdcma xdcmb x x x x x x 1 z z x x x x 0 1 0 1 1 x x x x 1 0 0 0 0 x x x x 1 1 0 0 0 x x x 0 0 0 0 0 0 0 0 x 1 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1 1 0 0 0 1 0 1 1 x 1 0 0 0 1 1 table 20. low-side out (lsout) drivers truth table (motor driver configured for h-bridge dc motor) note the lsout terminals are controlled by the out1 and out2 signals (bit 14 and bit 15 in the normal input frame). lsout is only available when motor driver c is confi gured as dc motor. (set bit 4 = 1 in config frame.) inputs output xdca xdcb xdcpwm outx rst i limit output tsd lsoutx x x x x x x 1 off x x x x 0 x 0 off x x x 0 1 0 0 off x x x 1 1 0 0 on x x x 1 1 1 0 limited
analog integrated circuit device data 32 freescale semiconductor 34921 functional device operation logic commands and registers table 21. high-side out (hsout) drivers truth table (motor driver configured for h-bridge dc motor) note: the hsout terminals are controlled by the out1 and out2 signals (bit 14 and bit 15 in the normal input frame). hsout is only available when dc motor is configured as motor driver c. (set bit 4 = 0 in config frame.) inputs output xdca xdcb xpwm outx rst i limit output tsd hsoutx x x x x x x 1 off x x x x 0 x 0 off x x x 0 1 0 0 off x x x 1 1 0 0 on x x x 1 1 1 0 limited table 22. step motor driver truth table (33) a or b bit a or b bit spwmx input i limit rst tsd output x output x x x x x x 1 off off x x x x 0 0 off off x x x 1 (34) 1 0 limited or off limited or off 0 0 x 0 1 0 off off 0 1 0 0 1 0 on off 0 1 1 0 1 0 off on 1 0 0 0 1 0 off on 1 0 1 0 1 0 on off 1 1 x 0 1 0 off off notes 33. to reduce parasitic dissipation associat ed with the body diode, the counterphase is turned on for synchronous rectification. 34. the current limit sense function may be disabled when the output s are disabled. hence, the output will oscillate between the requested state from the truth table and this state.
analog integrated circuit device data freescale semiconductor 33 34921 typical applications typical applications in typical applications such as a personal computer printer, the mc34921 would supply the motor drive and control for two bi- directional dc motors, two unidirectional dc motors, and one uni polar stepper motor. in addition, the mc34921 would supply the power management for the printer including: the system mcu core voltage , the 3.3v logic supply, an d the 5v logic supply. the mc34921 also would supply the system with the means to read a nd pre-process the carriage position information from an analog optical encoder. figure 15. typical application diagram supervisor circuitry 50 rst gate driver 27 gateout 22 vboost 23 cp2 26 cp1 0.1 f b+ + charge pump gate voltage generator 39 5 v 38 5 v supply 37 5 v switch 36 5 v select 5.0 v dual mode regulator 2 vcore select 13 vcore 12 vcore supply v core linear regulator 10 f 11 3.3 v 10 3.3 v switch +3.3 v 100 h b+ 3.3 v switching regulator 42 an0/analogout_a 43 an1/analogout_b 44 an2/analogin_a 45 an3/analogin_b a/d converter and multiplexer i/v converter 47 enc_filta 46 enc_filtb analog encoder gnd 1, 16, 17, 24, 32, 33, 41, 48, 49, 64 serial i/o dgnd b+ 10 f 560 f 7, 20, 21, 28, 29, 62 330 f 56 + ce sclk mosi miso 51 52 53 54 cpwma/cdcpwm 55 cpwmb 58 sb /lsout2 6 s b/lsout1 5 sa /cdcmb 4 s a/cdcma 3 active clamp step motor driver b+ cdcmb/hsout2 61 cdcma/hsout1 63 ss dc motor driver 18, 19 adcmb motor driver a b+ 14, 15 adcma apwm 59 30, 31 bdcmb motor driver b b+ 34, 35 bdcma bpwm 60 thermal shutdown oscillator
analog integrated circuit device data 34 freescale semiconductor 34921 package dimensions package dimensions for the most current revision of the package, visit www.freescale.com and do a keyword search using the 98a number for the specific device related to the data sheet. notes: 1. 2. 3. 4. 5. 6. 7. 8. dimensions are in inches. interpret dimensions and tolerances per asme y14.5m, 1994. datums a, b and d to be determined at seating plane c. dimensions d and e to be determined at seating plane c. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion 0.07 mm. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body sized dimensions including mold mismatch. exact shape of each corner is optional. these dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 64 0.2 h a-b d 1 49 48 17 16 32 33 b e/2 e e1 d1 d/2 d d1/2 3x view y 4x 4x 16 tips 0.2 c a-b d e1/2 a d pin 1 identifier ab ab e/2 e 60x x=a, b or d c l view y x s 0.05 z1 0.25 gage plane a2 (s) r (l1) l a1 view aa z r1 z2 4x seating plane a view aa 0.08 c z3 4x c h a-b m 0.08 d c 64x b j j b1 section ab-ab rotated 90? clockwise b c1 c plating base metal 8 8 8 8 millimeters 12.00 bsc 10.00 bsc 0.50 bsc 12.00 bsc 10.00 bsc 1.00 ref dim a a1 a2 b b1 c c1 d d1 e e e1 l l1 s f g z1 z2 z3 z r1 r2 min --- 0.05 1.35 0.17 0.17 0.09 0.09 0.45 6.00 0? 0? 0.20 6.00 0.08 0.08 11? 11? max 1.60 0.15 1.45 0.27 0.23 0.20 0.16 0.75 7.00 7? --- --- 7.00 --- --- 13? 13? g f view j-j exposed pad ae suffix (pb-free) 64-terminal lqfp exposed pad plastic package 98arh98426a issue 0
analog integrated circuit device data freescale semiconductor 35 34921 package dimensions notes
mc34921 rev 5.0 07/2005 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should a buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, the buyer shall i ndemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2005. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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